As is known in the art of semiconductor integrated circuits or “chips,” chips can be placed in s a stand-by or low power mode designed to save power in the system in which the chip resides. In this regard, and referring to FIG. 1, a first chip in a system (e.g., a microprocessor 8) might send a signal or signals to a second chip in a system (e.g., a dynamic random access memory (DRAM) 8) to inform the second chip to go into a low power state. In response, the second chip might disconnect or tri state certain circuit paths that draw current or shut off its internal clocks to save power.
Certain devices such as DRAMs can receive two system signals relevant to assuming a low power status. For example, two signals CKE (clock enable) and Vref (a reference voltage normally approximately half the power supply, or Vcc/2) can be input to the DRAM 9, and specifically are input to the input buffer circuitry 10 of FIG. 1. As shown, the input circuitry 10 consists of two differential amplifiers: a P-channel amplifier 11a, and a N-channel amplifier 11b. The outputs 15 of both differential amplifiers 11a, 11b are tied together, which is beneficial to compensate for potential inconsistencies in the N- and P-channels transistors which form the circuits. (However, in other applications, only one amplifier 11a, 11b individually could be used). In any event, the common output 15 of the amplifiers 11a, 11b (or single output if only one amplifier 11a, 11b is used), are typically sent to an inverter 14, which buffers the amplifier output to produce reliable Vcc (logic high; logic ‘1’) and ground (GND; logic low; logic ‘0’) signals (Vout) to the clocking circuitry of the DRAM (not shown).
As is well known, the differential amplifiers 11a, 11b compare the input signals Vref and CKE and seek to drive Vout to logic signals depending on the comparison. As illustrated, and generally speaking, when Vref>CKE, the output 15 of the amplifiers is a logic ‘1,’ and Vout from the inverter 14 is a logic ‘0,’ which is sent to the DRAM 9's clocking circuitry to indicate that the DRAM 9's clocks should be disabled and otherwise that the DRAM 9 should be placed in a low power mode. Conversely, when Vref<CKE, the output 15 of the amplifiers is a logic ‘0,’ and Vout from the inverter 14 is a logic ‘1,’ which is sent to activate the DRAM 9's clocking circuitry and otherwise to indicate that the DRAM should not be placed in a low power mode.
Thus, generally speaking, Vref>CKE indicates a low power condition for the DRAM 9, while Vref<CKE indicates that power is enabled. More specifically, when CKE is taken low by the system (i.e., <Vref), the clocks within the DRAM 9 are disabled, which causes the DRAM to draw less current, which saves system power.
In addition to taking CKE low to save power, several DRAM-based systems have investigated grounding Vref during DRAM self refresh to save system power. Thus, at certain times, Vref might also be taken low by the system as an additional system power saving measure.
However, the occurrence of CKE and Vref both being low can cause problems. First, if Vref=CKE=logic ‘0,’ the differential amplifiers 11a, 11b are potentially, and generally speaking, in a somewhat indeterminable state, as neither Vref nor CKE are obviously predominating over one another. More accurately, the differential amplifiers 11a, 11b may only change state when a small differential voltage, Δ, exists between Vref and CKE—i.e., the amplifiers change state and enters the low power condition when CKE+Δ<Vref, and enters the power enabled condition when CKE+Δ>Vref. This differential voltage Δ is difficult to control as it will vary from circuit to circuit depending on process or design variations in the fabrication of the DRAM 9.
Assume as shown in FIG. 4 that a small positive differential voltage, Δ, of 46 mV exists in some particular circuit of FIG. 1 due to processing variations. Because Δ is positive, when Vref=CKE=0V, the differential amplifier interprets these input voltages as calling for the DRAM 9 to be in a powered enabled mode. But clearly this is not what the system intended by sending Vref=CKE=0V; the system intended clocks to be disabled and that the DRAM 9 be placed in a low power mode.
Thus, the DRAM 9 enters a power enabled mode when the system has called for it to enter a low power mode. Obviously, this is not ideal, and the art would be benefited by a solution to this problem to allow for grounded Vref signals as an additional power saving measure in systems employing DRAMs (or other circuits) having input buffer circuitry 10 similar to that shown in FIG. 1.